The present disclosure relates generally an integrated circuit device and, more particularly, a method of forming a gate structure of an IC device.
As technology nodes decrease, semiconductor fabrication processes have introduced the use of gate dielectric materials having a high dielectric constant (e.g., high-k dielectrics). The high-k dielectrics exhibit a higher dielectric constant than the traditionally used silicon dioxide which allow for thicker dielectric layers to be used to obtain similar equivalent oxide thicknesses (EOTs). The processes also benefit from the introduction of metal gate structures providing a lower resistance than the traditional polysilicon gate structures. Therefore, transistors including gate structures having a high-k dielectric plus metal gate stack are advantageous.
However, fabrication processes providing for use of a high-k dielectric plus metal gate structure face challenges. For example, an interface layer may be required between the high-k gate dielectric layer (e.g., HfO2) and the substrate (e.g., Si) on which is it formed. The thickness of this interface layer also contributes to the EOT of the gate structure. Thus, as gate lengths decrease, controlling the thickness of the interface layer becomes more and more critical.
Therefore, what is needed is an improved method of forming a gate structure.